1. Technical Field
The present disclosure generally relates to semiconductor devices including MIS (metal-insulator-semiconductor) structures formed using a “vertical” device architecture in which a current flow may be controlled by electric field more efficiently on the basis a “buried” field plate.
2. Description of the Related Art
In the field of semiconductor devices immense progress has been achieved by reducing the dimensions of the circuit elements and improving associated process techniques and process tools. The continuous shrinkage of critical feature sizes has, at one cutting edge of the semiconductor technology, resulted in the fabrication of extremely complex integrated circuits which may comprise millions of transistor elements, which may be operated using extremely low supply voltages. On the other hand, the advances in materials, process techniques and process tools have also fuelled the development of complex integrated circuits, which comprise circuit elements such as transistors which are operated using moderately high voltages, i.e., from several volts to several hundred volts, possibly in combination with a more or less complex control circuitry including circuit elements that are to be operated on a very different potential. In the course of developing semiconductor devices including an increased number of individual circuit elements and/or circuit elements operated using high supply voltages, a wide variety of process technologies have been applied wherein field effect transistors have become a frequently used option in forming, for instance, very complex digital circuitry and high power circuitry due to certain advantages inherent to the field effect devices.
A field effect transistor comprises highly conductive semiconductor regions, typically referred to as drain and source regions, which are connected by a channel region in which a conductive channel may form upon applying an appropriate control voltage to a control electrode or gate electrode which is positioned close to the channel region and is separated therefrom by a thin insulating layer. The gate electrode structure, the insulation layer or gate dielectric layer and the adjacent semiconductor channel region thus define an MIS (metal-insulator-semiconductor) structure in order to establish a controlled current flow between the highly conductive drain and source regions through the controllable channel region. It should be appreciated that frequently the gate electrode structure may be provided in the form of a semiconductor material rather than using an actual “metal”, as indicated by the abbreviation MIS structure. Using a highly conductive semiconductor material instead of a metal may offer a plurality of advantages, for instance with respect to superior alignment of the gate electrode structure with respect to the drain and source regions, a pronounced temperature stability during the further processing and the like. Consequently, in the context of this application, the generic term “MIS structure” is to be understood such that this term also includes any field effect structures comprising a control electrode formed using a semiconductor material, such as a silicon material and the like.
When forming field effect transistors which are to be operated using high voltages, possibly in combination with a high drive current capability, typically a plurality of design concepts are implemented in order to provide transistors having said high drive current in combination with a high electric breakdown voltage, while at the same time the switching speed of the transistor is to reduce as much as possible. Consequently, great efforts are being made in improving the overall transistor characteristics, wherein in recent developments vertical transistor structures have been proposed in order to obtain a high breakdown voltage while reducing the overall lateral size of the corresponding transistor element.
In a typical vertical transistor configuration the drain terminal is provided at one surface of the semiconductor substrate while the source terminal is provided at the opposite surface of the semiconductor material so that a desirable distance in terms of a high breakdown voltage between the drain and source regions may be obtained using the thickness of the substrate material, thereby reducing the lateral size compared to any planar transistor configurations in which the drain and source regions are provided at the same surface of the semiconductor material. In the vertical transistor architecture a corresponding drain area of reduced doping concentration, which is typically referred to as a drift region, connects to a channel region which may have the same or an inverse doping compared to the drain and source region, depending on the overall transistor configuration. For example, in an enrichment type transistor structure the conductivity type of the drain and source regions may be inverse with respect to the connectivity type of the channel region. Thus, the source region, the channel region and the drain region including the drift region form a stacked “vertical” configuration wherein the conductivity of the channel region is controlled using a control electrode or gate electrode that has to be positioned in close proximity to the channel region. To this end, in recent vertical transistor architectures, the gate electrode may be provided, at least partially, in the form of a “buried” electrode which is thus formed in a recess or cavity provided in the semiconductor material, wherein the cavity is electrically insulated from the semiconductor base material by the gate dielectric material formed therein.
Generally, the dynamic behavior of a transistor configuration depends on a plurality of transistor parameters, wherein in particular the generally parasitic capacitance between the gate electrode structure and the drain terminal of the transistor may have a significant influence on the resulting switching speed. On the other hand, a certain degree of capacitive coupling of the gate electrode to the channel region should be preserved in order to provide controllability of the conductive channel that forms in the channel region upon applying an appropriate control voltage. To this end, the gate dielectric layer has to be provided, based on a given material composition, for instance provided in the form of a silicon dioxide material, with a specified thickness, which is typically a compromise between the desired capacitive coupling to the channel region and a desired high dielectric strength since, for instance, extremely different voltages are applied to the drain and source regions compared to the gate electrode structure.
In order to improve the dynamic behavior of a vertical transistor comprising a buried gate electrode structure it has been suggested to reduce the drain-gate capacitance by implementing an additional electrode structure below the actual gate electrode structure, which may thus act as a field plate that appropriately influences the electric field conditions, for instance by shielding the gate electrode structure from a portion of the drain region or a drift region. For example, the additional electrode may be electrically connected to the source region and provided thus a well-defined potential in the vicinity of the actual buried gate electrode structure, thereby “transforming” a part of the drain-gate capacitance into an increased drain-source capacitance. Consequently, by providing an additional field plate in combination with a buried gate electrode structure in vertical transistors, superior transistor characteristics may be achieved however at the cost of additional process complexity. Therefore, in many strategies it is attempted to reduce the number of additional process steps wherein in some well-established process techniques the process of forming the gate dielectric material and forming a dielectric material layer for electrically insulating the field plate from the actual gate electrode structure are applied as a common oxidation process which, however, may result in reduced electric strength and a reduced gain in performance with respect to the dynamic behavior, as will be described in more detail with reference to FIGS. 1a-1g. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 which represents a basic configuration of an MIS structure in the form of a vertical transistor. The device 100 comprises a crystalline semiconductor material which is provided in the form of several stacked semiconductor regions, as discussed above. As shown, a first semiconductor region 101, which may also be considered as a portion of a basic semiconductor substrate, has a high doping concentration and acts as a drain of the device 100, which in the example shown is provided in the form of a highly n-doped silicon material when the device 100 is to represent an enrichment-type n-channel transistor. Furthermore, a semiconductor region 102, which is referred to as a drift region, has an n-type conductivity, however based on a significantly reduced doping concentration compared to the highly doped drain region 101. Furthermore, a channel region 103, which is illustrated as a lightly p-doped area, connects to the drift region 102 and also connects to a highly doped source region 104. It should be appreciated that for convenience any contact regime for connecting to the drain and source regions 101, 104 are not illustrated in FIG. 1a. 
Moreover, a gate electrode structure 110 is provided in the form of a buried electrode structure and comprises a polysilicon electrode material 111, which is separated from the channel region 103 by a gate dielectric layer 112, which is typically provided in the form of a silicon dioxide material. Furthermore, the gate dielectric layer 112 also electrically insulates the electrode material 111 from the highly doped source region 104. Moreover, a further electrode structure 120, which may also be referred to as a field plate or field electrode, is provided below and partially adjacent to the gate electrode structure 110, wherein a moderately thick dielectric material 123, such as a silicon dioxide material, electrically isolates an electrode material 121, such as a polysilicon material, from the semiconductor region 102 and also partially from the electrode material 111. Moreover, a further dielectric layer 122, such as a silicon dioxide layer, electrically insulates a portion of the electrode material 121 that extends “into” the gate electrode structure 110 from the electrode material 111. Also in this case any additional interconnect regime for connecting the field plate 120 to any desired reference potential, such as the source potential that is connected to the source region 104 by any well-known contact regime, is not illustrated in FIG. 1a. Similarly, appropriate metallization regimes and interconnect structures are typically provided for connecting to the gate electrode structure 110, which are also not shown in FIG. 1a. 
The basic configuration of the device 100 as shown in FIG. 1a may result in a superior dynamic behavior since, for instance, the electrode structure 120, i.e., the electrode material 121 thereof, may efficiently shield the electrode material 111 from the drain potential, thereby reducing the drain-gate capacitance while increasing the drain-source capacitance. Consequently, a superior dynamic behavior, such as reduced switching times may be accomplished using the vertical transistor configuration as shown in FIG. 1a. The provision of the field plate electrode structure 120, however, involves additional process steps for locally forming the electrode material 121 and also providing the dielectric material 122. In conventional approaches in particular, forming the dielectric material 122 is combined with the process of forming the gate dielectric material 112 which, however, may result in increased probability of creating device failures or a non-reliable dielectric breakdown voltage, since upon forming the dielectric materials 112, 122 during a common oxidation process, the resulting layer thickness for these materials may be of comparable magnitude which, however, may give rise to certain device failures, as will be explained later on in more detail.
FIG. 1b schematically illustrates a portion of the structure 100 in an early manufacturing stage. As illustrated, a cavity 105, such as a trench or any other geometric element, is formed in the crystalline semiconductor material of the device 100 which, for convenience, is indicated as the semiconductor region 102 since, in some approaches, any other semiconductor regions, such as the channel region 103 and the highly doped source region 104, may not yet be provided. Furthermore, on any exposed surface areas of the crystalline semiconductor material 102 an insulating layer 123L is formed and comprises any appropriate dielectric material, such as silicon dioxide. The cavity 105 is formed using any well-established lithography techniques for providing an appropriate etch mask, which may then be used for etching into the crystalline semiconductor material 102 or which is used for patterning a hard mask material (not shown), which may then in turn be used for etching into the crystalline semiconductor material. Using a corresponding etch mask, the lateral position and size of the cavity 105 is defined, wherein the application of a substantially anisotropic etch recipe may thus result in a desired cross-sectional shape of the cavity 105. Appropriate etch recipes for etching a silicon material using plasma assisted etch techniques are well-established in the art. Next, the dielectric layer 123L is formed, for instance by deposition and/or oxidation, for instance using well-established process recipes such as CVD (chemical vapor deposition) using appropriate precursor materials, oxidation recipes and the like. The thickness of the layer 123L is selected such that it forms the dielectric material 123 of the field plate electrode structure 120 (cf. FIG. 1a) in order to appropriately isolate the electrode material 121 (cf. FIG. 1a) from the semiconductor material 102.
FIG. 1c schematically illustrates the device 100 in a further advanced stage in which a layer 121L of electrode material, for instance in the form of a polysilicon material, is deposited above the semiconductor material 102 and in the cavity 105. The layer 121L may be deposited using well-established low pressure CVD techniques and the like, possibly by incorporating a desired dopant species, such as phosphorous, during the deposition process in order to enhance the conductivity of the gate electrode to be formed from the layer 121L.
FIG. 1d schematically illustrates the device 100 when subjected to a material removal process 106, such as a CMP (chemical mechanical polishing) process, an etch process and the like, in order to remove material of the layer 121L (cf. FIG. 1c), thereby providing a substantially planar surface topography prior to the further processing. Planarizing the surface topography may provide for superior process conditions and thus process control and efficiency during the further processing, i.e., when removing a further portion of the electrode material 121 so as to define a desired height level for the gate electrode structure still to be formed.
FIG. 1e schematically illustrates the device 100 when exposed to a reactive etch ambient 107, in which the electrode material 121 is recessed within the cavity 105 as required for forming a buried gate electrode structure in the cavity 105. To this end, any selective etch process may be applied for which a plurality of wet chemical or plasma assisted etch recipes are available. For example, silicon material may efficiently be removed selectively with respect to silicon dioxide using wet chemistries, such as potassium hydroxide, tetra methyl ammonium hydroxide (TMAH) and the like, while also very efficient plasma assisted etch recipes based on hydrogen bromide and the like are available.
FIG. 1f schematically illustrates the device 100 in a further advanced stage in which a further material removal process 109, such as a wet chemical etch process, a plasma assisted etch process or a combination thereof is applied in order to remove an excess portion of the dielectric layer 123L (cf. FIG. 1e), thereby exposing a portion of the electrode material 121. As discussed above, the electrode material 121 is to be electrically insulated from a further electrode material that is still to be formed in the cavity 105. To this end, exposed surface areas of the material 121 have to be covered by a dielectric material, which is frequently formed in a process sequence in which also a gate dielectric material is formed on exposed sidewall surface areas of the cavity 105. In this case, in particular portions indicated as 120C of the field plate electrode 120 should be reliably covered by a dielectric material in order to provide for the desired dielectric strength of the electrode structure 120 with respect to the gate electrode structure still to be formed. To this end, a thickness of the dielectric material to be formed on exposed surface areas of the electrode material 121 should have a greater value compared to the gate dielectric material, which is to be provided with a specific thickness in order to comply with the overall transistor specifications, as also previously discussed. Although generally a polysilicon material may have a somewhat increased oxidation rate compared to the crystalline material of the semiconductor material 102, nevertheless a pronounced difference in the resulting layer thickness is difficult to achieve.
FIG. 1g schematically illustrates the semiconductor device 100 during an oxidation process 108 in which a gate dielectric material 112 is formed on exposed surface areas of the semiconductor region 102 while concurrently the dielectric material 122 is formed on exposed surface areas of the electrode material 121, wherein an average thickness 122T thereof may be somewhat greater, however, in the same order of magnitude as an average thickness 112T of the gate dielectric material 112. In particular, in the critical areas 120C, such as any corner areas, the local thickness may significantly deviate from the average thickness 122t, which may thus result in a reduced dielectric strength between the electrode material of the gate electrode structure 110 (cf. FIG. 1a) and the electrode material 121. Furthermore, the relatively low thickness 122t and in particular in combination with any local areas of further reduced thickness may contribute to an increased capacitive coupling, which may thus affect the dynamic behavior of the device 100.
Since basically an increased thickness of the layer 122 is desirable in order to ensure at least the same breakdown voltage between the gate electrode structure 110 and the filed plate electrode structure 120 as is obtained between the gate electrode structure 110 and the surrounding semiconductor areas, such as a source region still to be formed, additional process strategies have been proposed for increasing the average thickness 122T. For example, in some conventional approaches, the oxidation process 108 may be modified so as to result in an increased average thickness 122T, which may be accomplished by combining a dry oxidation ambient with a wet oxidation process which, however, may result in an overall reduced controllability of the entire oxidation process, thereby also resulting in less control of the finally obtained characteristics of the gate dielectric layer 112. Furthermore, generally the quality of the oxide material may be reduced compared to a dry oxidation process, thereby possibly also contributing to a degradation of transistor performance and/or uniformity of transistor characteristics. On the other hand, forming the layers 112 and 122 at least partially as separate dielectric materials may result in additional process complexity in terms of using one or more additional deposition steps in combination with further etch processes and the like, thereby contributing to significantly increased overall process complexity.